Wiring structure in a semiconductor device

ABSTRACT

A wiring structure includes a first wiring having a first wiring width, and a second wiring formed in the same layer as a layer in which the first wiring is formed, and having a second wiring width greater than the first wiring width. The second wiring is electrically connected to the first wiring. Both of the first and second wirings are composed of copper or an alloy predominantly containing copper therein. The first and second wirings have the same thickness as each other. A ratio of an area of the second wiring to an area of the first wiring is N:1 where N is equal to or greater than 2,000 and equal to or smaller than 200,000,000 (2,000≦N≦200,000,000).

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates to a wiring structure and a semiconductordevice including the wiring structure, and more particularly to adual-damascene wiring structure and a semiconductor device including thedual-damascene wiring structure.

[0003] 2. Description of the Related Art

[0004] In a conventional semiconductor device, a metal wire has beenusually composed of aluminum or aluminum alloy. This is because aluminumand aluminum alloy can be readily patterned through the use of aphotoresist mask and etching gas, since aluminum and aluminum alloy havea low resistivity.

[0005] In these days, with reduction in a size of a semiconductor deviceand increase in an operation rate of a semiconductor device, there is aneed for a material of which a wiring is to be composed and which has alower resistivity and a higher current density than aluminum andaluminum alloy. As a material meeting with such requirements, copper(Cu) draws much attention.

[0006] When a copper wiring is to be patterned, if a copper wiring isetched in the same manner as an aluminum wiring, copper is harmfullyaffected by etching gas and moisture, resulting in that corrosion occursinside the copper wiring. Accordingly, unlike an aluminum wiring, it isnot suitable to pattern a copper wiring through the use of a photoresistmask and etching gas.

[0007] As a method of patterning a copper wiring without occurrence ofcorrosion, there is known a damascene process. A damascene process is aprocess for forming a copper wiring on an underlying layer, includingsteps of forming a recess with an underlying layer, filling the recesswith copper, and polishing the copper for removal of unnecessaryportions of the copper.

[0008] When an upper wiring layer and a lower wiring layer areelectrically connected to each other in a multi-wiring layer structure,a via-hole is formed throughout an interlayer insulating film sandwichedbetween the upper and lower wiring layers, and then, a via-conductor isformed by filling the via-hole with electrical conductor such as metal.The upper and lower wiring layers are electrically connected to eachother through the thus formed via-conductor.

[0009] In this process, if the upper wiring layer and the via-conductorwere formed in separate steps, a time necessary for fabricating amulti-layer wiring structure would be increased. Hence, a dual-damasceneprocess is generally used in order to shorten the above-mentionedfabrication time. Herein, a dual-damascene process is a processincluding steps of filling both of a via-hole formed with an interlayerinsulating film and a recess formed with an upper wiring layer withmetal in a single common step, and polishing the metal such that themetal remains only in the via-hole and the recess, to thereby form avia-conductor.

[0010] In a dual-damascene process, a via-conductor is generallycomposed of copper, similarly to a damascene process.

[0011] It is known that a copper plating film has a lot of voids at asize of 10 nm or so. Such voids are agglomerated by migration, gather ata grain boundary, and develop into a larger void.

[0012] A plated copper has a grain larger than the same in a film formedby sputtering. As a result, grain having superior crystalline can beformed in plated copper. Such grain having superior crystalline is morelikely to be formed in a wiring layer having a greater width. This isbecause crystalline is degraded by a sidewall of a wiring layer. As aresult, a wiring layer having a small width often has inferiorcrystalline relative to a wiring layer having a great width. Theinventors found out that such difference in crystalline presented thefollowing facts by which voids were caused.

[0013] (a) Voids are more likely to be diffused in a wiring layer havinga greater width than in a wiring layer having a smaller width, becauseof superiority in crystalline of a wiring layer having a greater widthrelative to the same of a wiring layer having a smaller width.

[0014] (b) Since a wiring layer having a greater width has superiorityin crystalline relative to the same of a wiring layer having a smallerwidth, a wiring layer having a greater width has free energy smallerthan that of a wiring layer having a smaller width.

[0015] (c) Since a wiring layer having a greater width has superiorityin crystalline relative to the same of a wiring layer having a smallerwidth, grains a wiring layer having a smaller width are thermallyinstable than a wiring layer having a greater width with respect tosurface energy.

[0016] Due to the above-mentioned three facts, there occurs a phenomenonin which a volume moves towards a wiring layer having a great width froma wiring layer having a small width in dependence on annealing and asize. This phenomenon is called agglomeration.

[0017] The inventors found out that it would be effective to restrictenergy gradient in order to solve the agglomeration. Thus, the inventorspresent a solution to the problem that agglomeration occurs because awiring layer is connected to a thin wiring or a small via-contact independence on an area or a volume of the wiring layer.

[0018] Copper tends to be agglomerated, if annealed at a hightemperature. For instance, if a thin copper film were annealed at a hightemperature, the thin copper film would be agglomerated into a smallcircular piece. A thinner copper film is more likely to be agglomerated.A thin copper film having been agglomerated is no longer able to be usedas a material of which a copper wiring is composed. This is because, ifa copper film were agglomerated, the copper film would contain void, andresultingly, would have wiring defects such as breakage.

[0019] Hereinbelow are explained examples of wiring defects observed ina copper wiring fabricated in accordance with a conventionaldual-damascene process.

[0020]FIG. 1A is a cross-sectional view illustrating a first example ofa multi-layered wiring structure composed of copper.

[0021] First, a recess is formed at a surface of a lower insulatinglayer 104, and then, a lower copper wiring layer 105 is formed in therecess.

[0022] The lower copper wiring layer 105 is formed as follows, forinstance.

[0023] First, a barrier metal layer is deposited on an inner wall of therecess by sputtering. Then, the recess is filled with copper byelectrolytic plating. Then, copper deposited on the lower insulatinglayer 104 is removed by chemical mechanical polishing (CMP). Thus, thelower copper wiring layer 105 is formed just in the recess.

[0024] After the formation of the lower copper wiring layer 105, asilicon nitride (SiN) layer 106, a silicon dioxide (SiO₂) layer 107, asilicon nitride (SiN) layer 116 and a silicon dioxide (SiO₂) layer 117are formed as an interlayer insulating layer on the lower insulatinglayer 104 and the lower copper wiring layer 105.

[0025] Then, the interlayer insulating layer is formed with a via-hole108. The thus formed via-hole 108 is filled with resist. Thereafter, thesilicon nitride (SiN) layer 116 and the silicon dioxide (SiO₂) layer 117are removed in selected areas to thereby form a second recess in whichan upper wiring layer is to be formed.

[0026] Then, while the second recess and the via-hole 108 are keptexposed, a via-conductor 109 and an upper wiring layer 110 are formed ina common step. For instance, a barrier metal layer is deposited on innerwalls of the second recess and the via-hole 108 by sputtering, and then,a copper layer is formed over the barrier metal layer by electrolyticplating. Copper deposited on the silicon dioxide (SiO₂) layer 117 ispolished for removal.

[0027] Thus, there is formed a dual-damascene wiring comprised of thevia-conductor 109 and the upper wiring layer 110.

[0028] Then, an upper insulating layer comprised of a silicon nitride(SiN) layer 111 and a silicon dioxide (SiO₂) layer 112 is formed on theupper wiring layer 110.

[0029] As explained above, in a dual-damascene multi-layered wiringstructure, the via-conductor 109 through which the lower wiring layer105 and the upper wiring layer 110 are electrically connected to eachother is composed of the same material as a material of which the upperwiring layer 110 is composed. For instance, in the first exampleillustrated in FIG. 1A, both of the via-conductor 109 and the upperwiring layer 110 are composed of copper.

[0030] The above-mentioned dual-damascene multi-layered wiring structureis accompanied with a problem of void caused by the above-mentionedmigration of copper. Examples of void are illustrated in FIGS. 1B, 1Cand 1D.

[0031]FIG. 1B illustrates an example in which void 120B is observedalmost at the center of the via-hole 108. The void 120B observed almostat the center of the via-hole 108 electrically insulates the lowerwiring layer 105 and the upper wiring layer 110 from each other.

[0032]FIG. 1C illustrates an example in which void 120C is observed at abottom of the via-hole 108. The void 120C observed at a bottom of thevia-hole 108 electrically insulates the lower wiring layer 105 and theupper wiring layer 110 from each other, similarly to the void 120Billustrated in FIG. 1B.

[0033]FIG. 2 is a photograph of void generated at a bottom of avia-hole, taken through an electron-microscope.

[0034]FIG. 1D illustrates an example in which void 120D is observed atthe side of the lower wiring layer 105 at a boundary between thevia-conductor 109 and the lower wiring layer 105. Though the void 120Dis not generated inside the via-hole 108 unlike the voids 120B and 120Cillustrated in FIGS. 1B and 1C, the void 120D electrically insulates thelower wiring layer 105 and the upper wiring layer 110 from each other,similarly to the voids 120B and 120C illustrated in FIGS. 1B and 1C.

[0035]FIGS. 1A to 1C illustrate examples of voids observed in amulti-layered wiring structure which is a three-dimensional structure.Void is generated not only in a three-dimensional multi-layered wiringstructure, but also in a two-dimensional planar structure.

[0036]FIG. 3 is a plan view illustrating an example of a copper wiringstructure.

[0037] As illustrated in FIG. 3, a first wiring layer 121 having a firstwiring width W1 and a second wiring layer 122 having a second wiringwidth W2 greater than the first wiring width W1 are electricallyconnected to each other. The first wiring layer 121 and the secondwiring layer 122 are formed in a common layer, and have the samethickness as each other. The first wiring layer 121 and the secondwiring layer 122 are composed of copper.

[0038] In the copper wiring structure illustrated in FIG. 3, if a volumeof the second wiring layer 122 is significantly greater than a volume ofthe first wiring layer 121 (since the first wiring layer 121 and thesecond wiring layer 122 have the same thickness, “a volume” may bereplaced with “an area”) , copper is agglomerated inside the firstwiring layer 121. As a result, a tensile stress 123 directing towardsthe second wiring layer 122 from the first wiring layer 121 isgenerated, and thus, the second wiring layer 122 is absorbed into thefirst wiring layer 121.

[0039] As a result, void 124 is generated at an end of the first wiringlayer 121.

[0040] As explained so far, in both of a three-dimensional multi-layeredwiring structure and a two-dimensional planar wiring structure bothfabricated through a dual-damascene process, void is generated due tomigration of copper of which a wiring layer is composed, and the thusgenerated void causes electrical insulation between wiring layers.

[0041] Thus, many wiring structures have been suggested so far to avoidvoid caused by copper migration.

[0042] As an example of such a wiring structure, FIGS. 4A and 4Billustrate a damascene wiring structure suggested in Japanese UnexaminedPatent Publication No. 2001-298084 (A).

[0043]FIG. 4A is an upper plan view of the damascene wiring structuresuggested in the above-mentioned Publication, and FIG. 4B is across-sectional view taken along the line 4B-4B in FIG. 4A.

[0044] The illustrated damascene wiring structure is comprised of alower wiring layer 130, an interlayer insulating film 131 formed on thelower wiring layer 130, and an upper wiring layer. 132 (illustrated witha broken line) formed on the interlayer insulating film 131.

[0045] The interlayer insulating film 131 is formed at a surface thereofwith a recess 131 a, and further formed at a bottom of the recess 131 awith a via-hole 133 reaching the lower wiring layer 130. The via-hole133 has a diameter smaller than a width of the recess 131 a.

[0046] Around the via-hole 133 are formed four projections 134 upwardlyprojecting from a bottom of the recess 131 a. The projections 134 arecomposed of the same material as a material of which the interlayerinsulating film 131 is composed.

[0047] It is alleged in the above-mentioned Publication that thedamascene wiring structure illustrated in FIGS. 4A and 4B can avoiddefects caused by stress migration, typically such void generated in acopper wiring as mentioned above, even if a wiring had a long width,that is, a large volume.

[0048] However, the damascene wiring structure illustrated in FIGS. 4Aand 4B is accompanied with a problem that it has to carry out complexphotolithography and etching steps in order to form the projections 134,resulting in reduction in a fabrication yield.

[0049] In addition, since the projections 134 extend into the upperwiring layer 132 in the damascene wiring structure illustrated in FIGS.4A and 4B, it would be quite difficult to estimate a resistance of theupper wiring layer 132, and to analyze current concentration occurringin the upper wiring layer 132.

SUMMARY OF THE INVENTION

[0050] In view of the above-mentioned problems in the conventionalwiring structure, it is an object of the present invention to provide acopper wiring structure which is capable of avoiding generation of voidcaused by copper migration, and further avoiding electrical insulationbetween wiring layers.

[0051] Herein, a copper wiring structure includes not only athree-dimensional multi-layered wiring structure, but also atwo-dimensional planar wiring structure. Such a copper wiring structureis applicable to a semiconductor device, for instance.

[0052] In one aspect of the present invention, there is provided awiring structure including (a) a first wiring having a first wiringwidth, and (b) a second wiring formed in the same layer as a layer inwhich the first wiring is formed, and having a second wiring widthgreater than the first wiring width, the second wiring beingelectrically connected to the first wiring, wherein both of the firstand second wirings are composed of copper or an alloy predominantlycontaining copper therein, the first and second wirings have the samethickness as each other, and a ratio of an area of the second wiring toan area of the first wiring is N:1 where N is equal to or greater than2,000 and equal to or smaller than 200,000,000 (2,000≦N≦200,000,000).

[0053] As will be explained in detail later, if the first and secondwirings have the same thickness as each other, it is possible to avoidmigration of copper in the first wiring, and hence, generation of voidin the first wiring, by setting the area ratio N equal to or greaterthan 2,000 and equal to or smaller than 200,000,000(2,000≦N≦200,000,000).

[0054] In accordance with the above-mentioned wiring structure, it isnot necessary to form such a pattern as the projections 134 of thedamascene wiring structure suggested in the above-mentioned JapaneseUnexamined Patent Publication No. 2001-298084. Hence, it is possible toavoid copper migration in a thin wiring layer through simplifiedfabrication steps.

[0055] It is preferable that the area ratio N is equal to or greaterthan 2,000 and equal to or smaller than 2,000,000 (2,000≦N≦2,000,000).

[0056] It is preferable that each of the first and second wirings has athickness equal to or greater than 150 nm and equal to or smaller than650 nm.

[0057] For instance, the first wiring width may be designed to be equalto or smaller than 0.28 micrometers, 0.20 micrometers, 0.14 micrometersor 98 nanometers.

[0058] As an alternative, the first wiring width may be designed to bein the range of 0.28±10.04 micrometers, 0.20±0.04 micrometers, 0.14±0.04micrometers or 98±0.04 nanometers.

[0059] If the second wiring width is equal to or greater than 1.12micrometers and the first wiring has a length equal to or smaller than0.56 micrometers, it is preferable that the first wiring width is equalto or greater than 0.28 micrometers.

[0060] There are suitable combinations in a width and a length of thefirst wiring.

[0061] For instance, it is preferable that the first wiring width isequal to 0.14 micrometers, and the first wiring has a length equal to orgreater than about 0.40 micrometers.

[0062] As an alternative, it is preferable that the first wiring widthis equal to 0.20 micrometers, and the first wiring has a length equal toor greater than about 0.20 micrometers.

[0063] As an alternative, it is preferable that the first wiring widthis equal to 0.28 micrometers, and the first wiring has a length equal toor greater than about 0.19 micrometers.

[0064] One of parameters for suppressing copper migration is atemperature at which copper is to be annealed. In accordance with theexperiments the inventors had conducted, it was found out that it waspreferable that the first and second wirings were annealed at atemperature of 150 degrees centigrade or higher, if the first and secondwirings were composed of copper.

[0065] It was also found out that a wiring layer might be annealed at alower temperature by mixing metals other than copper with copper ofwhich a wiring layer is composed, that is, by composing a wiring layerof copper alloy. Hence, if the first and second wirings are composed ofan alloy predominantly containing copper therein, the first and secondwirings may be annealed at a temperature higher than a temperature atwhich the first and second wirings are annealed if the first and secondwirings are composed of copper.

[0066] The wiring structure may be designed to have a dual-damascenestructure.

[0067] There is further provided a wiring structure including an upperwiring layer, and a lower wiring layer electrically connected to theupper wiring layer through a via-contact, wherein all of the upperwiring layer, the lower wiring layer and the via-contact are composed ofcopper or an alloy predominantly containing copper therein, and a ratioof a volume of the upper or lower wiring layer to a volume of thevia-contact is N:1 where N is equal to or greater than 3 and equal to orsmaller than 200,000,000 (3≦N≦200,000,000).

[0068] As will be explained in detail later, if the first and secondwirings have different thicknesses from each other, it is possible toavoid migration of copper in the first wiring, and hence, generation ofvoid in the first wiring, by setting the area ratio N equal to orgreater than 3 and equal to or smaller than 200,000,000(3≦N≦200,000,000).

[0069] In accordance with the above-mentioned wiring structure, it isnot necessary to form such a pattern as the projections 134 of thedamascene wiring structure suggested in the above-mentioned JapaneseUnexamined Patent Publication No. 2001-298084. Hence, it is possible toavoid copper migration in a thin wiring layer through simplifiedfabrication steps.

[0070] It is preferable that the volume ratio N is equal to or greaterthan 2,000 and equal to or smaller than 2,000,000 (2,000≦N≦2,000,000).

[0071] There is further provided a wiring structure including an upperwiring layer, and a lower wiring layer electrically connected to theupper wiring layer through a via-contact, wherein all of the upperwiring layer, the lower wiring layer and the via-contact are composed ofcopper or an alloy predominantly containing copper therein, and assumingthat a ratio of a volume of the upper or lower wiring layer to a volumeof the via-contact is N:1, if the ratio N is equal to or greater than3.5 and equal to or smaller than 2,000,000 (3.5≦N≦2,000,000), the upperwiring layer is electrically connected to the lower wiring layer throughat least two via-contacts.

[0072] The via-contact may be designed to have a circular cross-sectionas well as a square cross-section.

[0073] When the via-contact is designed to have a circularcross-section, it is preferable that the via-contact has a diameterequal to or smaller than 0.28 micrometers, it is more preferable thatthe via-contact has a diameter equal to or smaller than 0.20micrometers, it is further more preferable that the via-contact has adiameter equal to or smaller than 0.14 micrometers, and it is mostpreferable that the via-contact has a diameter equal to or smaller than98 nanometers.

[0074] The above-mentioned diameters of the via-contact may havetolerance of ±0.04 micrometers. Specifically, when the via-contact isdesigned to have a circular cross-section, a diameter of the via-contactis preferably 0.28±0.04 micrometers, more preferably 0.20±0.04micrometers, further more preferably 0.14±0.04 micrometers, and mostpreferably 98 nanometers ±0.04 micrometers.

[0075] There is still further provided a wiring structure including anupper wiring layer, and a lower wiring layer electrically connected tothe upper wiring layer through a via-contact, wherein all of the upperwiring layer, the lower wiring layer and the via-contact are composed ofcopper or an alloy predominantly containing copper therein, and assumingthat a ratio of a volume of the upper or lower wiring layer to a volumeof the via-contact is N:1, if the via-contact has a circularcross-section having a diameter of 0.14±0.04 micrometers, the ratio N isequal to or smaller than three (3).

[0076] There is yet further provided a wiring structure including anupper wiring layer, and a lower wiring layer electrically connected tothe upper wiring layer through a via-contact, wherein all of the upperwiring layer, the lower wiring layer and the via-contact are composed ofcopper or an alloy predominantly containing copper therein, and assumingthat a ratio of a volume of the upper or lower wiring layer to a volumeof the via-contact is N:1, if the via-contact has a circularcross-section having a diameter of 0.20±0.04 micrometers, the ratio N isequal to or smaller than nine (9).

[0077] There is still yet further provided a wiring structure includingan upper wiring layer, and a lower wiring layer electrically connectedto the upper wiring layer through a via-contact, wherein all of theupper wiring layer, the lower wiring layer and the via-contact arecomposed of copper or an alloy predominantly containing copper therein,and assuming that a ratio of a volume of the upper or lower wiring layerto a volume of the via-contact is N:1, if the via-contact has a circularcross-section having a diameter of 0.28±0.04 micrometers, the ratio N isequal to or smaller than fifteen (15).

[0078] It is preferable that the upper and lower wiring layers areannealed at a temperature equal to or higher than 150 degreescentigrade. If the upper and lower wiring layers are composed of analloy predominantly containing copper therein, it is preferable that theupper and lower wiring layers are annealed at a temperature higher thana temperature at which the upper and lower wiring layers are annealed ifthe upper and lower wiring layers are composed of copper.

[0079] If the via-contact is designed to be square in a cross-section,it is preferable that a side of the via-contact is equal to or smallerthan 3 micrometers.

[0080] There is further provided a wiring structure including an upperwiring layer, and a lower wiring layer electrically connected to theupper wiring layer through a via-contact, wherein all of the upperwiring layer, the lower wiring layer and the via-contact are composed ofcopper or an alloy predominantly containing copper therein, and a wiringwidth of each of said upper and lower wiring layers is defined by amaximum diameter of a circle inscribed with said via-contact, saidcircle having a center identical with a center of said via-contact.

[0081] For instance, it is preferable that the maximum wiring width isequal to 3 micrometers.

[0082] The wiring structure in accordance with the present invention isapplicable to a semiconductor device, for instance.

[0083] The advantages obtained by the aforementioned present inventionwill be described hereinbelow.

[0084] The present invention makes it possible to avoid generation ofvoid caused by migration of copper in the first wiring, and hence,further avoid electrical insulation between wiring layers not only in athree-dimensional multi-layered copper wiring structure, but also in atwo-dimensional planar copper wiring structure. Accordingly, a device towhich the wiring structure in accordance with the present invention isapplied, such as a semiconductor device, could have enhancedreliability.

[0085] The above and other objects and advantageous features of thepresent invention will be made apparent from the following descriptionmade with reference to the accompanying drawings, in which likereference characters designate the same or similar parts throughout thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0086]FIGS. 1A, 1B, 1C and 1D are cross-sectional views illustratingconventional wiring structures.

[0087]FIG. 2 is a photograph of void generated at a bottom of avia-hole, taken through an electron-microscope.

[0088]FIG. 3 is a plan view illustrating void generated in aconventional copper wiring structure.

[0089]FIG. 4A is an upper plan view of a conventional damascene wiringstructure.

[0090]FIG. 4B is a cross-sectional view taken along the line 4B-4B inFIG. 4A.

[0091]FIG. 5 is a plan view of a wiring structure in accordance with thefirst embodiment of the present invention.

[0092]FIG. 6 is a perspective view of the wiring structure illustratedin FIG. 5.

[0093]FIG. 7 is a perspective view of a variant of the wiring structureillustrated in FIG. 5.

[0094]FIG. 8 is a plan view of a wiring structure used in theexperiment.

[0095]FIG. 9 is a cross-sectional view taken along the line IX-IX inFIG. 8.

[0096]FIG. 10 is a graph showing the results of the experiment.

[0097]FIG. 11A is a graph showing the results of the experiment.

[0098]FIG. 11B is a graph showing the results of the experiment.

[0099]FIG. 12A is an upper view of upper and lower wiring layers.

[0100]FIG. 12B is a cross-sectional view of a via-contact with a circledescribed so as to be inscribed with a cross-section of the via-contact.

[0101]FIG. 12C is another cross-sectional view of a via-contact with acircle described so as to be inscribed with a cross-section of thevia-contact.

[0102]FIG. 13A is a plan view of a wiring structure in accordance withthe second embodiment of the present invention.

[0103]FIG. 13B is a cross-sectional view taken along the line 12B-12B inFIG. 13A.

[0104]FIG. 14 is a graph showing a relation between a width of avia-conductor and a non-defectiveness rate.

[0105]FIGS. 15A to 15D are cross-sectional views of a wiring structure,illustrating respective steps of a method of fabricating the same.

[0106]FIG. 16 is a graph showing a relation between a size of avia-conductor and a non-defectiveness rate.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0107] Preferred embodiments in accordance with the present inventionwill be explained hereinbelow with reference to drawings.

[0108] [First Embodiment]

[0109]FIG. 5 is an upper plan view of a wiring structure 10 inaccordance with the first embodiment of the present invention, and FIG.6 is a perspective view of the wiring structure 10 illustrated in FIG.5.

[0110] For instance, the wiring structure 10 can be applied to asemiconductor device as a part of a planar wiring pattern.

[0111] The wiring structure 10 is comprised of a first wiring layer 11,and a second wiring layer 12 electrically and physically connected tothe first wiring layer 11. The first and second wiring layers 11 and 12are formed in a common layer, and both composed of copper (Cu).

[0112] As illustrated in FIGS. 5 and 6, the first wiring layer 11 has alength L1, a width W1 and a height H1, and the second wiring layer 12has a length L2, a width W2 and a height H2. The width W2 of the secondwiring layer 12 is greater than the width W1 of the first wiring layer11 (W2>W1)

[0113] A volume V1 of the first wiring layer 11 and a volume V2 of thesecond wiring layer 12 are calculated as follows.

V1=L1×W1×H1

V2=L2×W2×H2

[0114] If the volume V2 is significantly greater than the volume V1(V2>>V1), copper of which the first wiring layer 11 is composed isagglomerated, and hence, the first wiring layer 11 having the volume V1is absorbed into the second wiring layer 12 having the volume V2,resulting generation of void at an end of the first wiring layer 11.

[0115] In view of this problem, the inventors had conducted theexperiments in order to find a critical ratio between the volumes V1 andV2 at which copper of which the first wiring layer 11 is notagglomerated, that is, the first wiring layer 11 is not absorbed intothe second wiring layer 12.

[0116] In accordance with the results of the experiments, it was foundout that it was possible to avoid migration of copper in the firstwiring layer 11, and hence, absorption of the first wiring layer 11 intothe second wiring layer 12 by setting a ratio N equal to or greater than2,000, but equal to or smaller than 200,000,000 (2,000≦N≦200,000,000)where the ratio N is defined as V2/V1.

[0117] It was also found out that an optimal range in the ratio N was2,000 to 2,000,000 among the above-mentioned range of 2,000 to200,000,000 in the ratio N.

[0118] As illustrated in FIG. 7, if the height H1 of the first wiringlayer 11 and the height H2 of the second wiring layer 12 are set equalto a height H (H=H2=H), the volume ratio N defined as V2/V1 isequivalent to an area ratio between areas of the first and second wiringlayers 11 and 12. That is, the ratio N may be defined as L2·W2/L1·W1.

[0119] Accordingly, if the heights H1 and H2 are equal to a height H(H1=H2=H), the length L1 and the width W1 of the first wiring layer 11and the length L2 and the width W2 of the second wiring layer 12 aredetermined so that the ratio N is defined as follows:

2,000≦N=L2·W2/L1·W1≦200,000,000.

[0120] Hereinbelow are explained the experiment for determining a rangeof the ratio N, and the results thereof.

[0121]FIG. 8 is a plan view of the wiring structure used in theexperiment, and FIG. 9 is a cross-sectional view taken along the lineIX-IX in FIG. 8.

[0122] As illustrated in FIG. 9, the experimental wiring structure wascomprised of a plurality of lower wiring layers 15 arranged in a line,and a plurality of upper wiring layers 17 each arranged between theadjacent lower wiring layers 15, and each electrically connecting theadjacent lower wiring layers 15 to each other through via-holes 16.

[0123] Each of the lower wiring layers 15 was designed to have the samestructure as the structure of the wiring structure 10 illustrated inFIGS. 5 and 7. Specifically, each of the lower wiring layers 15 wascomprised of a first wiring layer 15 a, and a second wiring layer 15 belectrically and physically connected to the first wiring layer 15 a.The first and second wiring layers 15 a and 15 b were formed in a commonlayer, and both composed of copper (Cu).

[0124] The second wiring layer 15 b had a length L2 of 3.0 micrometers,and a width W2 of 3.0 micrometers.

[0125] On the other hand, a length L1 of the first wiring layer 15 a wasvaried among 0.14 micrometers, 0.27 micrometers, 0.55 micrometers and1.12 micrometers. In addition, a width W1 of the first wiring layer 15 awas varied among 0.14 micrometers, 0.20 micrometers and 0.28 micrometersfor each of the above-mentioned four lengths L1. That is, there wereformed twelve wiring structures in which the first wiring layers 15 ahad different lengths L1 and widths W1 from one another.

[0126] Then, a non-defectiveness rate was measured for each of thetwelve wiring structures.

[0127]FIG. 10 is a graph showing a non-defectiveness rate in each of thetwelve wiring structures.

[0128] As is obvious in view of FIG. 10, the greater the length L1 is,the higher a non-defectiveness rate is when the width W1 is set equal toeither 0.14 micrometers, 0.20 micrometers or 0.28 micrometers.

[0129] If an allowable non-defectiveness rate is set equal to or greaterthan 80%, it is understood in view of FIG. 10 that the length L1 isnecessary to be equal to or greater than about 0.40 micrometers, whenthe width W1 is set equal to 0.14 micrometers.

[0130] It is also understood in view of FIG. 10 that the length L1 isnecessary to be equal to or greater than about 0.20 micrometers, whenthe width W1 is set equal to 0.20 micrometers, and that the length L1 isnecessary to be equal to or greater than about 0.19 micrometers, whenthe width W1 is set equal to 0.28 micrometers.

[0131] It was further found out in the experiment that the first wiringlayer 15 a could have the width W1 equal to or smaller than 98nanometers.

[0132] Though the width W1 was set equal to 0.14 micrometers, 0.20micrometers, 0.28 micrometers or 98 nanometers in the above-mentionedexperiment, it was also found out in the experiment that the width W1had a tolerance of ±0.04 micrometers. Hence, the length L1 is necessaryto be in the above-mentioned preferable ranges also when the width W1 isequal to 0.14±0.04 micrometers, 0.20±0.04 micrometers, 0.28±0.04micrometers or 98 nanometers ×0.04 micrometers.

[0133] It was also found out that the width W1 of the first wiring layer15 a was preferably equal to or greater than 0.28 micrometers when thewidth W2 of the second wiring layer 15 b was equal to or greater than1.12 micrometers and the length L1 of the first wiring layer 15 a wasequal to or smaller than 0.56 micrometers.

[0134] For the wiring structure including the first wiring layer 15 ahaving the length L1 of 0.14 micrometers, the wiring structure includingthe first wiring layer 15 a before annealed and the wiring structureincluding the first wiring layer 15 a having been annealed at 150degrees centigrade were both measured with respect to anon-defectiveness rate. As is obvious in view of FIG. 10, anon-defectiveness rate is slightly lowered in the wiring structureincluding the first wiring layer 15 a having been annealed at 150degrees centigrade.

[0135] In view of the above-mentioned experimental results, the volumeratio N defined as V2/V1 is preferably in the range of 2,000 and200,000,000 both inclusive, and more preferably in the range of 2,000and 2,000,000 both inclusive.

[0136] As mentioned above, void is generated in the first wiring layer11 or 15 a due to migration of copper of which the first wiring layer 11or 15 a is composed. Copper is agglomerated in accordance with aplurality of parameters. One of such parameters is a temperature atwhich the first wiring layer is heated and a thickness of the firstwiring layer.

[0137] Accordingly, the inventors had conducted the experiment to findsuch a temperature and a thickness at which copper is not agglomerated.

[0138] In the experiment, the first wiring layer 15 a and the secondwiring layer 15 b were heated at room temperature (RT), 50 degreescentigrade, 100 degrees centigrade, 150 degrees centigrade, 200 degreescentigrade, 300 degrees centigrade and 400 degrees centigrade, and adistance between copper molecules was measured at each of thetemperatures.

[0139]FIGS. 11A and 11B are graphs showing the results of theexperiment. FIG. 11A shows the results of the experiment having beencarried out to the second wiring layer 15 b having a relatively largearea, and FIG. 11B shows the results of the experiment having beencarried out to the first wiring layer 15 a having a relatively smallarea. In FIGS. 11A and 11B, an axis of ordinate indicates an existencerate of copper molecule, and an abscissa indicates a distance betweencopper molecule and a reference point in the unit of angstrom.

[0140] In FIGS. 11A and 11B, a peak indicates that copper moleculeexists at the peak, and a height of a peak indicates an existence rateof copper molecule. As is obvious in view of FIGS. 11A and 11B, peaksare found at distances of about 2.2 angstroms, about 4.1 angstroms andabout 4.8 angstroms. Accordingly, copper molecule exists at thosedistances.

[0141] The peaks are clearly observed at a temperature equal to orsmaller than 100 degrees centigrade. In contrast, the peaks are notclearly observed at a temperature of 150 degrees centigrade or higher.This means that if annealed at a temperature equal to or greater than150 degrees centigrade, copper molecules would significantly thermallyoscillate, and accordingly, copper molecules would much obtain mobility,resulting in that copper molecules do not tend to be agglomerated, inother words, void is not likely to be generated.

[0142] Accordingly, it is understood that in order to prevent generationof void in the first wiring layer 15 a, it is preferable that the firstwiring layer 15 a is annealed at a temperature equal to or greater than150 degrees centigrade.

[0143] It was also found out that a preferable range of a thickness T ofthe first and second wiring layers 15 a and 15 b is 150 nanometers to650 nanometers (150 nm≦T≦650 nm).

[0144] The first wiring layer 15 a is composed of copper in theabove-mentioned experiment. The first wiring layer 15 a may be composedof not only copper, but also a copper alloy containing copperpredominantly.

[0145] For instance, the first wiring layer 15 a may be composed of acopper alloy such as Cu—Al, Cu—Sn, Cu—Ag, Cu—Cr, Cu—Ti, Cu—Co or Cu—Mg.A mixture ratio of copper and other metals is determined in accordancewith parameters such as a temperature at which the first wiring layer 15a is to be annealed, a width, a length and a thickness of each of thefirst and second wiring layers 15 a and 15 b.

[0146] As mentioned above, it is preferable that the first wiring layer15 a is annealed at a temperature equal to or greater than 150 degreescentigrade in order to prevent generation of void in the first wiringlayer 15 a. This is the case only when the first wiring layer 15 a iscomposed only of copper.

[0147] The inventors have found out that the first wiring layer 15 a isnecessary to be annealed at a temperature higher than 150 degreescentigrade, if the first wiring layer 15 a is composed of a copperalloy.

[0148] Specifically, if each of the first and second wiring layers 15 aand 15 b is composed of a copper alloy predominantly containing coppertherein, the first and second wiring layers 15 a and 15 b may beannealed at a temperature higher than a temperature at which the firstand second wiring layers 15 a and 15 b composed of copper is to beannealed.

[0149] The inventors had further found out a relation between a size ofthe via-contact 16 and an optimal width of the upper wiring layer 17 andthe lower wiring layer 15 in the wiring structure illustrated in FIG. 9.

[0150] Specifically, it is preferable that a width of the upper andlower wiring layers 17 and 15 is set equal to a maximum diameter of acircle inscribed with the via-contact 16, in which the circle has acenter identical with a center of the via-contact 16.

[0151]FIG. 12A is an upper view of the upper and lower wiring layers 17and 15, FIG. 12B is a cross-sectional view of the via-contact 16, andFIG. 12C is another cross-sectional view of the via-contact 16.

[0152] With reference to FIG. 12B, when the via-contact 16 has a squarecross-section, a circle 16A is described in such a way that the circle16A has a center identical with a center of the via-contact 16 and thecircle 16A is inscribed with the via-contact 16. Assuming the thusdescribed circle 16A has a diameter D, a width W of the upper and lowerwiring layers 17 and 15 is defined so as to be equal to or smaller thanthe diameter D, as illustrated in FIG. 12A.

[0153] As illustrated in FIG. 12C, if the via-contact 16 has arectangular cross-section, a circle 16A is described such that thecircle 16A is inscribed with longer sides of the rectangular via-contact16. Then, the diameter D of the circle 16A is determined.

[0154] In accordance with the experiments conducted by the inventors,the diameter D is preferably equal to 3 micrometers.

[0155] [Second Embodiment]

[0156]FIGS. 13A and 13B illustrate a wiring structure 20 in accordancewith the second embodiment of the present invention.

[0157]FIG. 13A is a plan view of the wiring structure 20, and FIG. 13Bis a cross-sectional view taken along the line 12B-12B in FIG. 13A.

[0158] The wiring structure 20 is applicable to a multi-layered wiringstructure in a semiconductor device, for instance.

[0159] The wiring structure 20 in accordance with the second embodimentis comprised of a first lower wiring layer 21 a, a second lower wiringlayer 21 b, an upper wiring layer 22 arranged above and across the firstand second lower wiring layers 21 a and 21 b, a first via-conductor 23 aelectrically connecting the first lower wiring layer 21 a and the upperwiring layer 22 to each other, and a second via-conductor 23 belectrically connecting the second lower wiring layer 21 b and the upperwiring layer 22 to each other.

[0160] The first and second lower wiring layers 21 a and 21 b, the upperwiring layer 22 and the first and second via-conductors 23 a and 23 bare all composed of copper.

[0161] The first and second lower wiring layers 21 a and 21 b have thesame structure as the structure of the wiring structure 10 in accordancewith the first embodiment, illustrated in FIGS. 4 and 7.

[0162] The upper wiring layer 22 has rectangular longitudinal andlatitudinal cross-sections. That is, the upper wiring layer 22 is a cubein shape, and has a volume V2.

[0163] The first and second via-conductors 23 a and 23 b have an almostsquare latitudinal cross-section. That is, each of the first and secondvia-conductors 23 a and 23 b is a cube in shape, and has a volume V1.

[0164] As mentioned earlier, if the volume V2 is significantly greaterthan the volume V1 (V2>>V1), copper of which the first and secondvia-conductors 23 a and 23 b are composed is agglomerated, and hence,the first and second via-conductors 23 a and 23 b each having the volumeV1 is absorbed into the upper wiring layer 22 having the volume V2,resulting generation of void in the first and second via-conductors 23 aand 23 b.

[0165] In view of this problem, the inventors had conducted theexperiments in order to find a critical ratio between the volumes V1 andV2 at which copper of which the first and second via-conductors 23 a and23 b are not agglomerated, that is, the first and second via-conductors23 a and 23 b are not absorbed into the upper wiring layer 22.

[0166] In the above-mentioned first embodiment, the volume ratio N wasdetermined in a two-dimensional planar wiring structure. In contrast, inthe second embodiment, a volume ratio N is determined in athree-dimensional multi-layered wiring structure.

[0167] In a two-dimensional planar wiring structure, copper of which awiring layer is composed is agglomerated in two directions, that is, Xand Y directions. In contrast, in a three-dimensional multi-layeredwiring structure, copper of which a wiring layer is composed isagglomerated in three directions, that is, X, Y and Z directions.Accordingly, mechanism of copper migration and a critical volume ratio Nin a three-dimensional multi-layered wiring structure is slightlydifferent from those in a two-dimensional planar wiring structure.

[0168] In accordance with the results of the experiments, it was foundout that it was possible to avoid migration of copper in the first andsecond via-conductors 23 a and 23 b, and hence, absorption of the firstand second via-conductors 23 a and 23 b into the upper wiring layer 22by setting a volume ratio N equal to or greater than 3, but equal to orsmaller than 200,000,000 (3≦N≦200,000,000) where the volume ratio N isdefined as V2/V1.

[0169] It was also found out that an optimal range in the volume ratio Nwas 2,000 to 2,000,000 among the above-mentioned range of 3 to200,000,000 in the volume ratio N.

[0170] Furthermore, the inventors considered that if the first andsecond via-conductors 23 a and 23 b were designed to have a squarecross-section, they would have an optimal length of a side of the squarecross-section. Hence, the inventors had conducted experiment in order tofind such an optimal length of a side of the square cross-section.

[0171]FIG. 14 is a graph showing the results of the experiment. In FIG.14, an abscissa indicates a length of a side of a square cross-section,and an axis of ordinate indicates a non-defectiveness rate of a wiringstructure.

[0172] As is obvious in view of FIG. 14, if a length of a side of thesquare cross-section is equal to or smaller than 3 micrometers, anon-defectiveness rate remains almost 100%. In contrast, if a length ofa side of the square cross-section is over 3 micrometers, anon-defectiveness rate is decreased. For instance, if a length of a sideof the square cross-section is equal to 20 micrometers, anon-defectiveness rate is decreased down to about 28%.

[0173] As is obvious in view of the explanation having been made above,it is necessary that a length of a side of the square cross-section ofthe first and second via-conductors 23 a and 23 b is equal to or smallerthan 3 micrometers, in order to keep a non-defectiveness rate at 100%.

[0174] A non-defectiveness rate is about 80% when a length of a side ofthe square cross-section of the first and second via-conductors 23 a and23 b is equal to 4 micrometers. Accordingly, it is necessary that alength of a side of the square cross-section of the first and secondvia-conductors 23 a and 23 b is equal to or smaller than 4 micrometers,in order to keep a non-defectiveness rate at 80%.

[0175] When the volume ratio N is equal to or greater than 3.5, butequal to or smaller than 2,000,000 (3.5≦N≦2,000,000) in the case thatthe upper wiring layer 22 is electrically connected to the first andsecond lower wiring layers 23 a and 23 b through the singlevia-conductor 23 a and 23 b, it would be preferable that the upperwiring layer 22 is electrically connected to the first lower wiringlayer 21 a or the second lower wiring layer 21 b through two or morevia-contacts.

[0176] As is obvious in FIG. 14, it was found out that the yield couldbe enhanced by forming two or move via-contacts. In FIG. 14, each of thevia-contacts is designed to have a diameter of 0.14 micrometers.

[0177] When agglomeration as one of physical phenomenon takes place,metal atoms move such that surface energy is minimized. Inagglomeration, if an area of a larger volume having lower energy than anarea of a smaller volume in question becomes larger, the area of asmaller volume would have smaller stability. Accordingly, in order tosuppress agglomeration, it would be preferable to have a countermeasureagainst a physically infinite volume. In this sense, it would bepreferable to format least two via-contacts.

[0178] The upper limit number of via-holes can be experimentallydetermined.

[0179] Though the first and second lower wiring layers 23 a and 23 b aredesigned to have a square cross-section in the above-mentioned example,the first and second lower wiring layers 23 a and 23 b may be designedto have a circular cross-section.

[0180] When the first and second lower wiring layers 23 a and 23 b aredesigned to have a circular cross-section, the results of theexperiments having been conducted by the inventors indicate that adiameter of the circular cross-section is preferably equal to or smallerthan 0.28 micrometers, more preferably equal to or smaller than 0.20micrometers, further more preferably equal to or smaller than 0.14micrometers, and most preferably equal to or smaller than 98 nanometers.

[0181] The above-mentioned diameters of the first and second lowerwiring layers 23 a and 23 b may have tolerance of ±0.04 micrometers.Specifically, when the first and second lower wiring layers 23 a and 23b is designed to have a circular cross-section, a diameter of the firstand second lower wiring layers 23 a and 23 b is preferably 0.28±0.04micrometers, more preferably 0.20±0.04 micrometers, further morepreferably 0.14±0.04 micrometers, and most preferably 98 nanometers±0.04 micrometers.

[0182] As mentioned later, a preferable volume ration N varies independence on a diameter of the first and second lower wiring layers 23a and 23 b.

[0183] Hereinbelow is explained an example of a wiring structure towhich the wiring structure 20 in accordance with the second embodimentis applied, with reference to FIGS. 15A to 15D.

[0184] First, as illustrated in FIG. 15A, an electrically insulatingfilm 32 is formed on a silicon substrate 31 on which a transistor (notillustrated) and a contact (not illustrated) have been already formed.

[0185] Then, a SiN₄ film 33 is formed on the electrically insulatingfilm 32 by the thickness of about 50 nanometers. Then, a planarizedinsulating film 34 comprised of a silicon dioxide film is formed on theSiN₄ film 33 by the thickness of about 400 nanometers.

[0186] Then, an inversely-patterned resist mask 35 is formed on theplanarized insulating film 34 by photolithography and etching.

[0187] Then, as illustrated in FIG. 15B, the silicon dioxide film 34 isetched through the resist mask 35 to thereby form a recess 34 a.

[0188] After removal of the resist mask 35, as illustrated in FIG. 15C,a refractive metal film 35A containing nitrogen therein, such as a TaNfilm, is formed all over the silicon dioxide film 34 and an exposedportion of the SiN₄ film 33 by the thickness of about 20 nanometers.

[0189] Then, copper 36 is deposited over the refractive metal film 35Aby the thickness of about 0.1 micrometers.

[0190] Then, a copper film 37 is formed on the copper 36 by thethickness of 100 nanometers by sputtering.

[0191] Then, a copper film 38 is formed on the copper film 37 by thethickness of 800 nanometers by plating.

[0192] Then, the copper films 38 and 37, the copper 36 and therefractive metal film 35 are etched back by chemical mechanicalpolishing (CMP). Thus, there is obtained such a wiring structure asillustrated in FIG. 15D.

[0193] The inventors had estimated that the preferable volume ratio N inthe wiring structure 20 illustrated in FIGS. 13A and 13B varied independence on a volume of the first or second via-conductor 23 a or 23b, and had conducted the experiment to verify the estimate.

[0194] The results of the experiment are shown in FIG. 16. FIG. 16 is agraph showing a relation between a volume ratio N and anon-defectiveness rate in the wiring structure 20 illustrated in FIGS.13A and 13B in the case that the first or second via-conductor 23 a or23 b is designed to have a circular cross-section.

[0195] In the experiment, four first via-conductors 23 a having acircular cross-section were formed. They had diameters of 0.14micrometers, 0.20 micrometers, 0.28 micrometers and 0.40 micrometers. Anon-defectiveness rate was measured for each of the four firstvia-conductors 23 a while the volume ratio N was gradually varied.

[0196] As illustrated in FIG. 16, thermal stress was increased and anon-defectiveness rate was lowered for the first via-conductor 23 ahaving a smaller diameter.

[0197] In the first via-conductor 23 a having a diameter of 0.14micrometers, a non-defectiveness rate remained 100% when the volumeratio N was equal to or smaller than three (3), but a non-defectivenessrate was decreased, if the volume ratio N was over three (3).

[0198] Accordingly, it was found out that the volume rate N waspreferably equal to or smaller than three (3) when the firstvia-conductor 23 a was designed to have a circular cross-section havinga diameter of 0.14 micrometers.

[0199] In the first via-conductor 23 a having a diameter of 0.20micrometers, a non-defectiveness rate remained 100% when the volumeratio N was equal to or smaller than nine (9), but a non-defectivenessrate was decreased, if the volume ratio N was over nine (9).

[0200] Accordingly, it was found out that the volume rate N waspreferably equal to or smaller than nine (9) when the firstvia-conductor 23 a was designed to have a circular cross-section havinga diameter of 0.20 micrometers.

[0201] In the first via-conductor 23 a having a diameter of 0.28micrometers, a non-defectiveness rate remained 100% when the volumeratio N was equal to or smaller than fifteen (15), but anon-defectiveness rate was decreased, if the volume ratio N was overfifteen (15).

[0202] Accordingly, it was found out that the volume rate N waspreferably equal to or smaller than fifteen (15) when the firstvia-conductor 23 a was designed to have a circular cross-section havinga diameter of 0.28 micrometers.

[0203] With respect to the first via-conductor 23 a having a diameter of0.40 micrometers, a non-defectiveness rate remained 100% independentlyof the volume rate N within a range of the volume rate N having beenmeasured in the experiment.

[0204] Accordingly, it is considered that when the first via-conductor23 a is designed to have a circular cross-section having a diameter of0.40 micrometers, the volume rate N can be set equal to any rate withoutany restriction.

[0205] The same results as mentioned above were obtained, even if thediameters of the first via-conductor 23 a , that is, 0.14 micrometers,0.20 micrometers, 0.28 micrometers and 0.40 micrometers had an error of±0.04 micrometers. Accordingly, when the first via-conductor 23 a isdesigned to have a diameter of 0.14±0.04 micrometers, 0.20±0.04micrometers, 0.28±0.04 micrometers or 0.40±0.04 micrometers, the volumerate N may be set equal to or smaller than 3, 9 and 15, and equal to anyrate, respectively.

[0206] It should be noted that a ratio having been explained above for athree-dimensional structure may be applied to a two-dimensionalstructure.

[0207] While the present invention has been described in connection withcertain preferred embodiments, it is to be understood that the subjectmatter encompassed by way of the present invention is not to be limitedto those specific embodiments. On the contrary, it is intended for thesubject matter of the invention to include all alternatives,modifications and equivalents as can be included within the spirit andscope of the following claims.

[0208] The entire disclosure of Japanese Patent Application No.2001-051803 filed on Feb. 27, 2001 including specification, claims,drawings and summary is incorporated herein by reference in itsentirety.

What is claimed is:
 1. A wiring structure comprising: (a) a first wiringhaving a first wiring width; and (b) a second wiring formed in the samelayer as a layer in which said first wiring is formed, and having asecond wiring width greater than said first wiring width, said secondwiring being electrically connected to said first wiring, wherein bothof said first and second wirings are composed of copper or an alloypredominantly containing copper therein, said first and second wiringshave the same thickness as each other, and a ratio of an area of saidsecond wiring to an area of said first wiring is N:1 where N is equal toor greater than 2,000 and equal to or smaller than 200,000,000(2,000≦N≦200,000,000).
 2. The wiring structure as set forth in claim 1,wherein said ratio N is equal to or greater than 2,000 and equal to orsmaller than 2,000,000 (2,000≦N≦2,000,000).
 3. The wiring structure asset forth in claim 1, wherein each of said first and second wirings hasa thickness equal to or greater than 150 nm and equal to or smaller than650 nm.
 4. The wiring structure as set forth in claim 1, wherein saidfirst wiring width is equal to or smaller than 0.28 micrometers.
 5. Thewiring structure as set forth in claim 1, wherein said first wiringwidth is equal to or smaller than 0.20 micrometers.
 6. The wiringstructure as set forth in claim 1, wherein said first wiring width isequal to or smaller than 0.14 micrometers.
 7. The wiring structure asset forth in claim 1, wherein said first wiring width is equal to orsmaller than 98 nanometers.
 8. The wiring structure as set forth inclaim 1, wherein said first wiring width is in the range of 0.28±0.04micrometers.
 9. The wiring structure as set forth in claim 1, whereinsaid first wiring width is in the range of 0.20±0.04 micrometers. 10.The wiring structure as set forth in claim 1, wherein said first wiringwidth is in the range of 0.14±0.04 micrometers.
 11. The wiring structureas set forth in claim 1, wherein said first wiring width is in the rangeof 98 nanometers ±0.04 micrometers.
 12. The wiring structure as setforth in claim 1, wherein said first wiring width is equal to or greaterthan 0.28 micrometers, if said second wiring width is equal to orgreater than 1.12 micrometers and said first wiring has a length equalto or smaller than 0.56 micrometers.
 13. The wiring structure as setforth in claim 1, wherein said first wiring width is equal to 0.14micrometers, and said first wiring has a length equal to or greater thanabout 0.40 micrometers.
 14. The wiring structure as set forth in claim1, wherein said first wiring width is equal to 0.20 micrometers, andsaid first wiring has a length equal to or greater than about 0.20micrometers.
 15. The wiring structure as set forth in claim 1, whereinsaid first wiring width is equal to 0.28 micrometers, and said firstwiring has a length equal to or greater than about 0.19 micrometers. 16.The wiring structure as set forth in claim 1, wherein said first andsecond wirings are annealed at a temperature of 150 degrees centigradeor higher, if said first and second wirings are composed of copper. 17.The wiring structure as set forth in claim 1, wherein if said first andsecond wirings are composed of an alloy predominantly containing coppertherein, said first and second wirings are annealed at a temperaturehigher than a temperature at which said first and second wirings areannealed if said first and second wirings are composed of copper. 18.The wiring structure as set forth in claim 1, wherein said wiringstructure has a dual-damascene structure.
 19. A wiring structureincluding an upper wiring layer, and a lower wiring layer electricallyconnected to said upper wiring layer through a via-contact, wherein allof said upper wiring layer, said lower wiring layer and said via-contactare composed of copper or an alloy predominantly containing coppertherein, and a ratio of a volume of said upper or lower wiring layer toa volume of said via-contact is N:1 where N is equal to or greater than3 and equal to or smaller than 200,000,000 (3≦N≦200,000,000).
 20. Thewiring structure as set forth in claim 19, wherein said ratio N is equalto or greater than 2,000 and equal to or smaller than 2,000,000(2,000≦N≦2,000,000).
 21. The wiring structure as set forth in claim 19,wherein said via-contact has a substantially circular cross-sectionhaving a diameter equal to or smaller than 0.28 micrometers.
 22. Thewiring structure as set forth in claim 19, wherein said via-contact hasa substantially circular cross-section having a diameter equal to orsmaller than 0.20 micrometers.
 23. The wiring structure as set forth inclaim 19, wherein said via-contact has a substantially circularcross-section having a diameter equal to or smaller than 0.14micrometers.
 24. The wiring structure as set forth in claim 19, whereinsaid via-contact has a substantially circular cross-section having adiameter equal to or smaller than 98 nanometers.
 25. The wiringstructure as set forth in claim 19, wherein said via-contact has asubstantially circular cross-section having a diameter in the range of0.28±0.04 micrometers.
 26. The wiring structure as set forth in claim19, wherein said via-contact has a substantially circular cross-sectionhaving a diameter in the range of 0.20±0.04 micrometers.
 27. The wiringstructure as set forth in claim 19, wherein said via-contact has asubstantially circular cross-section having a diameter in the range of0.14±0.04 micrometers.
 28. The wiring structure as set forth in claim19, wherein said via-contact has a substantially circular cross-sectionhaving a diameter in the range of 98 nanometers ±0.04 micrometers. 29.The wiring structure as set forth in claim 19, wherein said upper andlower wiring layers are annealed at a temperature equal to or higherthan 150 degrees centigrade.
 30. The wiring structure as set forth inclaim 19, wherein if said upper and lower wiring layers are composed ofan alloy predominantly containing copper therein, said upper and lowerwiring layers are annealed at a temperature higher than a temperature atwhich said upper and lower wiring layers are annealed if said upper andlower wiring layers are composed of copper.
 31. The wiring structure asset forth in claim 19, wherein said via-contact has a squarecross-section a side of which has a length equal to or smaller than 3micrometers.
 32. A wiring structure including an upper wiring layer, anda lower wiring layer electrically connected to said upper wiring layerthrough a via-contact, wherein all of said upper wiring layer, saidlower wiring layer and said via-contact are composed of copper or analloy predominantly containing copper therein, and assuming that a ratioof a volume of said upper or lower wiring layer to a volume of saidvia-contact is N:1, if said ratio N is equal to or greater than 3.5 andequal to or smaller than 2,000,000 (3.5≦N≦2,000,000), said upper wiringlayer is electrically connected to said lower wiring layer through atleast two via-contacts.
 33. The wiring structure as set forth in claim32, wherein said via-contact has a substantially circular cross-sectionhaving a diameter equal to or smaller than 0.28 micrometers.
 34. Thewiring structure as set forth in claim 32, wherein said via-contact hasa substantially circular cross-section having a diameter equal to orsmaller than 0.20 micrometers.
 35. The wiring structure as set forth inclaim 32, wherein said via-contact has a substantially circularcross-section having a diameter equal to or smaller than 0.14micrometers.
 36. The wiring structure as set forth in claim 32, whereinsaid via-contact has a substantially circular cross-section having adiameter equal to or smaller than 98 nanometers.
 37. The wiringstructure as set forth in claim 32, wherein said via-contact has asubstantially circular cross-section having a diameter in the range of0.28±0.04 micrometers.
 38. The wiring structure as set forth in claim32, wherein said via-contact has a substantially circular cross-sectionhaving a diameter in the range of 0.20±0.04 micrometers.
 39. The wiringstructure as set forth in claim 32, wherein said via-contact has asubstantially circular cross-section having a diameter in the range of0.14±0.04 micrometers.
 40. The wiring structure as set forth in claim32, wherein said via-contact has a substantially circular cross-sectionhaving a diameter in the range of 98 nanometers ±0.04 micrometers. 41.The wiring structure as set forth in claim 32, wherein said upper andlower wiring layers are annealed at a temperature equal to or higherthan 150 degrees centigrade.
 42. The wiring structure as set forth inclaim 32, wherein if said upper and lower wiring layers are composed ofan alloy predominantly containing copper therein, said upper and lowerwiring layers are annealed at a temperature higher than a temperature atwhich said upper and lower wiring layers are annealed if said upper andlower wiring layers are composed of copper.
 43. The wiring structure asset forth in claim 32, wherein said via-contact has a squarecross-section a side of which has a length equal to or smaller than 3micrometers.
 44. A wiring structure including an upper wiring layer, anda lower wiring layer electrically connected to said upper wiring layerthrough a via-contact, wherein all of said upper wiring layer, saidlower wiring layer and said via-contact are composed of copper or analloy predominantly containing copper therein, and assuming that a ratioof a volume of said upper or lower wiring layer to a volume of saidvia-contact is N:1, if said via-contact has a circular cross-sectionhaving a diameter of 0.14±0.04 micrometers, said ratio N is equal to orsmaller than three (3).
 45. The wiring structure as set forth in claim44, wherein said upper and lower wiring layers are annealed at atemperature equal to or higher than 150 degrees centigrade.
 46. Thewiring structure as set forth in claim 44, wherein if said upper andlower wiring layers are composed of an alloy predominantly containingcopper therein, said upper and lower wiring layers are annealed at atemperature higher than a temperature at which said upper and lowerwiring layers are annealed if said upper and lower wiring layers arecomposed of copper.
 47. The wiring structure as set forth in claim 44,wherein said via-contact has a square cross-section a side of which hasa length equal to or smaller than 3 micrometers.
 48. A wiring structureincluding an upper wiring layer, and a lower wiring layer electricallyconnected to said upper wiring layer through a via-contact, wherein allof said upper wiring layer, said lower wiring layer and said via-contactare composed of copper or an alloy predominantly containing coppertherein, and assuming that a ratio of a volume of said upper or lowerwiring layer to a volume of said via-contact is N:1, if said via-contacthas a circular cross-section having a diameter of 0.20±0.04 micrometers,said ratio N is equal to or smaller than nine (9).
 49. The wiringstructure as set forth in claim 48, wherein said upper and lower wiringlayers are annealed at a temperature equal to or higher than 150 degreescentigrade.
 50. The wiring structure as set forth in claim 48, whereinif said upper and lower wiring layers are composed of an alloypredominantly containing copper therein, said upper and lower wiringlayers are annealed at a temperature higher than a temperature at whichsaid upper and lower wiring layers are annealed if said upper and lowerwiring layers are composed of copper.
 51. The wiring structure as setforth in claim 48, wherein said via-contact has a square cross-section aside of which has a length equal to or smaller than 3 micrometers.
 52. Awiring structure including an upper wiring layer, and a lower wiringlayer electrically connected to said upper wiring layer through avia-contact, wherein all of said upper wiring layer, said lower wiringlayer and said via-contact are composed of copper or an alloypredominantly containing copper therein, and assuming that a ratio of avolume of said upper or lower wiring layer to a volume of saidvia-contact is N:1, if said via-contact has a circular cross-sectionhaving a diameter of 0.28±0.04 micrometers, said ratio N is equal to orsmaller than fifteen (15).
 53. A wiring structure including an upperwiring layer, and a lower wiring layer electrically connected to saidupper wiring layer through a via-contact, wherein all of said upperwiring layer, said lower wiring layer and said via-contact are composedof copper or an alloy predominantly containing copper therein, and awiring width of each of said upper and lower wiring layers is defined bya maximum diameter of a circle inscribed with said via-contact, saidcircle having a center identical with a center of said via-contact. 54.The wiring structure as set forth in claim 53, wherein said maximumdiameter is equal to 3 micrometers.
 55. A semiconductor device includinga wiring structure comprising: (a) a first wiring having a first wiringwidth; and (b) a second wiring formed in the same layer as a layer inwhich said first wiring is formed, and having a second wiring widthgreater than said first wiring width, said second wiring beingelectrically connected to said first wiring, wherein both of said firstand second wirings are composed of copper or an alloy predominantlycontaining copper therein, said first and second wirings have the samethickness as each other, and a ratio of an area of said second wiring toan area of said first wiring is N:1 where N is equal to or greater than2,000 and equal to or smaller than 200,000,000 (2,000≦N≦200,000,000).56. A semiconductor device including a wiring structure comprising anupper wiring layer, and a lower wiring layer electrically connected tosaid upper wiring layer through a via-contact, wherein all of said upperwiring layer, said lower wiring layer and said via-contact are composedof copper or an alloy predominantly containing copper therein, and aratio of a volume of said upper or lower wiring layer to a volume ofsaid via-contact is N:1 where N is equal to or greater than 3 and equalto or smaller than 200,000,000 (3≦N≦200,000,000).
 57. A semiconductordevice including a wiring structure comprising an upper wiring layer,and a lower wiring layer electrically connected to said upper wiringlayer through a via-contact, wherein all of said upper wiring layer,said lower wiring layer and said via-contact are composed of copper oran alloy predominantly containing copper therein, and assuming that aratio of a volume of said upper or lower wiring layer to a volume ofsaid via-contact is N:1, if said ratio N is equal to or greater than 3.5and equal to or smaller than 2,000,000 (3.5≦N≦2,000,000), said upperwiring layer is electrically connected to said lower wiring layerthrough two via-contacts.
 58. A semiconductor device including a wiringstructure comprising an upper wiring layer, and a lower wiring layerelectrically connected to said upper wiring layer through a via-contact,wherein all of said upper wiring layer, said lower wiring layer and saidvia-contact are composed of copper or an alloy predominantly containingcopper therein, and a wiring width of each of said upper and lowerwiring layers is defined by a maximum diameter of a circle inscribedwith said via-contact, said circle having a center identical with acenter of said via-contact.